The present invention relates to a floating gate memory device and method of making the same. More particularly, the present invention relates to a floating gate memory device having a lower capacitance and more uniform tunneling characteristics between the floating gate and a control gate, and a method of making the device.
One type of semiconductor memory device is a metal-oxide-semiconductor (MOS) device having a floating gate, in which the charge is stored, insulated from a semiconductor substrate, generally by a layer of silicon oxide, and a second or control gate over the floating gate and insulated therefrom, generally by a layer of silicon oxide. The control gate generally extends across the sidewalls of the floating gate as well as over the outer surface of the floating gate. One type of such a floating gate memory device uses the Fowler-Nordheim tunneling effect to cause a flow of electrons onto the floating gate from the control gate through the intermediate silicon oxide layer to charge the floating gate and to cause the flow of electrons from the floating gate to the control gate to discharge the floating gate. Charging or discharging the floating gate is achieved by applying a relatively high voltage of the appropriate polarity between the control gate and the substrate and tailoring the capacitance between the floating gate and each of the substrate and the control gate so that a larger portion of the voltage drop is between the control gate and the floating gate than between the substrate and the floating gate. Thus, it is desirable to have a low capacitance between the floating gate and the control gate so that the capacitive coupling between the two gates will induce higher voltages therebetween.
There are a number of factors which effect the capacitance between the two gates. One factor is the thickness of the insulating layer between the gates. Although thicker insulating layers provide lower capacitance, thicker layers require a corresponding increase in the voltages for charging or discharging the floating gate. Therefore, it would be desirable to be able to provide a relatively thick insulating layer which has enhanced conduction at lower fields to satisfy both the voltage limitations and the capacitance requirements. Another factor to be considered is that the control gate extends across the sidewalls of the floating gate as well as over the outer surface of the floating gate so that the capacitance between the sidewalls of the floating gate and the control gate contribute to the overall capacitance between the two gates. With the present trend to making the gates narrower to achieve higher circuit density, the thickness of the floating gate approaches its width dimension so that the sidewall capacitance becomes a major portion of the overall capacitance. In addition, variations in the thickness of the floating gate which may result from manufacturing process variations would then result in major changes in the capacitance between the two gates.
Another problem with regard to the operation of the floating gate memory device, particularly when using polycrystalline silicon for the gates, arises from the fact that the conduction properties of silicon oxide grown over polycrystalline silicon are asymmetrical. By asymmetrical it is meant that the oxide is far more conductive when the control gate is positive, i.e. the flow of electrons is from the floating gate to the control gate, then when the floating gate is positive, i.e. the flow of electrons is from the control gate to the floating gate. Thus, the voltage required to cause electron conduction from the control gate to the floating gate is generally much higher than the voltage required to cause electron conduction from the floating gate to the control gate. For the successful operation of floating gate memory devices that operate on the principle of charge transfer as described above, it would be desirable to have both voltages equal or at least as close as possible.
This difference in operating voltages results from the fact that the silicon oxide grown on a polycrystalline silicon layer causes the surface of the polycrystalline silicon layer to be textured, whereas the outer surface of the oxide layer, on which the outer polycrystalline silicon layer is deposited, is relatively smoother. The textured surface has hillochs which act as pointed emitters to create high fields when the inner polycrystalline silicon layer is negative with respect to the outer polycrystalline silicon layer so that it provides high electron conduction from the inner layer to the outer layer. However, the inner surface of the outer polycrystalline silicon layer is smoother so that for the same applied field, the conduction from the outer layer to the inner layer is substantially lower.
In my copending patent application, Ser. No. 505,728, filed June 20, 1983, now abandoned, there is described a structure and method of making it which alleviates this problem by making the inner surface of the outer polycrystalline silicon layer textured, with undulations which substantially follow the undulations of the textured surface of the inner polycrystalline silicon layer. Thus, both polycrystalline silicon layer have hillochs which act as emitters to increase the conduction in both directions between the two layers.